DPUs: Handling the Difficult Tasks in the SOC Dataplane
Designers have long understood how to use a single processor for the control functions in an SOC design. However, there are a lot of data-intensive functions that control processors cannot handle. That's why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and verify, and are not programmable to handle multiple standards or changes.
Designers often want to use programmable functions in the dataplane, and only Tensilica offers the core technology that overcomes the top four objections to using processors in the dataplane:
- Data throughput - All other processor cores use bus interfaces to transfer data. Tensilica allows designers to bypass the main bus entirely, directly flowing data into and out of the execution units of the processor using a FIFO-like (first in-, first out) process, just like a block of RTL.
- Fit into hardware design flow - Tensilica is the only processor core company that provides glueless pin-level co-simulation of the ISS (instruction set simulator) with Verilog simulators from Cadence, Synopysys and Mentor. Using existing tools, designers can simulate the processor in the context of the entire chip. And Tensilica offers a better verification infrastructure over RTL, with pre-verified state machines.
- Processing speed - Tensilica's patented automated tools help the designer customize the processor for the application, like video, audio, or communications. This lets designers use Tensilica's processors to get 10 to 100 times the processing speed of traditional processors and DSPs
- Customization challenges - Most designers are not processor experts, and are hesitant to customize a processor architecture for their needs. With Tensilica's automated processor generator, designers can quickly and safely get the customized processor core for their exact configuration.
The Best of CPUs and DSPs with Better Performance
Dataplane Processor Units (DPUs) combine the best of CPUs and DSPs with much better performance and fit for each application.
DPUs Deliver Best of CPU and DSP at 10-100x Performance
DPUs are designed to handle performance-intensive DSP (audio, video, imaging, and baseband signal processing) and embedded RISC processing functions (security, networking, and deeply embedded control).
Used Throughout the Chip
Tensilica's DPUs offer a unique blend of CPU + DSP strengths and deliver programability, low power, optimized performance, and small core size. DPUs are employed throughout the chip:
Lower Design Risk Than RTL
The inherent programability in Tensilica's processor cores enables performance tuning and bug fixes via firmware upgrade, lowering design risk and allowing faster time to market. Tensilica pre-verifies all changes made to the processor, and guarantees that your processor design will be correct by construction. You don't actually have to get in there and make the processor changes yourself - our automated tools will take your guidance and make the changes for you, correctly.
Fundamentally Different from Standard CPUs and DSPs
Here are the fundamental differences between Tensilica's DPUs and traditional processors and DSPs:
|Traditional Processors & DSPs||Tensilica DPUs (Dataplane Processors)|
|Processors and DSPs are fixed function, generic, non-optimized||Customizable processors provide a unique combination of optimized processor plus DSP|
|Changing or designing a processor is expensive, difficult and risky. Requires a team of 50+ processor designers.||Fully automated processor and software tools creation. One algorithm expert or SOC designer can create a customized core in less than one hour.|
|Processors and DSPs offer limited power and performance||Tensilica processors can outperform traditional DSPs and CPUs by 10x or more in power and performance|
|I/O bottlenecks render processors and DSPs inappropriate for dataplane processing and are difficult to integrate with RTL||Tensilica's processors have unlimited user defined I/Os, mimicking RTL-style hardware dataflows for easy RTL integration|
|No differentiation: same hardware and in many cases software||Reduce design risk while capturing proprietary knowledge into a customized implementation|
Automated Dataplane Processor:
Create a Core & Software in Less than 1 Hour
Tensilica has automated much of the risk out of creating a customized dataplane processor. Using our tools, designers can create a customized core and matching software tools in less than an hour.
Tensilica has automated the process of creating customized dataplane processors.
Find out more about how to customize our processors in our Product section.
Direct I/O Into and Out of the Processor
All other processor cores and DSPs use bus interfaces to transfer data. Tensilica allows designers to bypass the main bus entirely, directly flowing data into and out of the execution units of the processor using a FIFO-like (first in-, first out) process. We provide three ways of directly communicating, much like an RTL block. You can use our TIE Queues for FIFO connections, our TIE Ports for GPIO-like connections, and TIE Lookup interfaces for fast, easy connections to memories.
Flexible I/O Allows Much Faster Inter-block Communication