Diamondコントローラ


Diamondコントローラを次世代のSOC設計に

今日の複雑なコンシューマーエレクトロニクスのシステムは、メインのシステムCPUから取り除かれた、おびただしい数の組み込み制御タスクがデータプレーンに存在します。例えば、今日の最先端のスマートフォンの設計では、20個程度の組み込みコントローラが使用されています。そこでは、WiFiやBluetooth、NFC、LTE、3Gのプロトコルスタックの実行や、複雑なビデオおよびイメージングタスクのハンドリング、セキュリティの管理などが行われています。

テンシリカのDPUは、組み込み制御タスクの処理に優れています。Diamond Standardファミリのコントローラは、Xtensa DPUを代表するコンフィギュレーションのショーケースとして設計されました。したがって、どの定義済みDiamond Standardコントローラを使用しても、または独自のタスクに最適化したコントローラをビルドしても、テンシリカは最適なコントローラソリューションを提供できます。

Diamond Standardファミリは、極小のキャッシュレスコントローラから高性能な3並列VLIW CPUまで、様々な範囲の要件に応えます。

次世代のコントローラ設計のスタート地点としての5コア

スタート地点としてサンプルとなる、コントローラのコンフィギュレーションが5種類定義されています。

  • Diamond Standard 106Micro - 極小のキャッシュレスコントローラ
  • Diamond Standard 108Mini - ミドルサイズのキャッスレスコントローラ。DSP命令搭載
  • Diamond Standard 212GP - キャッシュ搭載のミッドレンジコントローラ。DSP命令も搭載
  • Diamond Standard 233L - Linux用のミッドレンジコントローラ
  • Diamond Standard 570T - リアルタイムアプリケーション向きの高性能3並列VLIW DSP

詳細はFeaturesタブをご参照ください。

Which Diamond Standard Controller is Right for Your Application?

Tensilica's Diamond Standard processor family covers the broadest range of performance of any embedded computing architecture. Here is a feature chart to help you figure out which processor core is best for your needs.

Diamond Selector Guide

  106Micro108Mini212GP233L570T
Pipeline stages 5 5 5 5 5
Instruction width (bits) 16/24 16/24 16/24 16/24` 16/24/64
Multiple instruction issue (static superscalar) no no no no 3 issue or 2 issue
Local memory data path width (bits) 32 32 32 32 64
General purpose registers 32 32 32 32 32
Instruction cache size N/A N/A 8 Kbyte 16 Kbyte 16 Kbyte
I-Cache associativity N/A N/A 2-way 4-way 2-way
Data cache size N/A N/A 8 Kbyte 16 Kbyte 16 Kbyte
D-Cache associativity N/A N/A 2-way 4-way 2-way
Local instruction RAM, user selectable size, maximum size 128 Kbyte 128 Kbyte 128 Kbyte N/A 128 Kbyte
Local data RAM, user selectable size, maximum size 128 Kbyte 128 Kbyte (dual) 128 Kbyte N/A 128 Kbyte
XLMI Interface no no yes no yes
Input/output ports (32 bits wide) no yes yes yes yes
Input/output queues (32 bits wide) no no no no yes
System interface (PIF) width 32 32 32 32 64
MUL 16 yes yes yes yes yes
MAC 16-bit single cycle no no yes yes yes
32x32 MUL32 yes yes yes yes dual
32-bit integer divide no yes yes yes yes
Sign Extend, NSA, MIN/MAX yes yes yes yes yes
Zero-overhead looping no no yes yes yes
External interrupts 12 16 16 16 16
Timer interrupts 1 3 3 3 3
Software interrupts 1 2 2 2 2
Non-maskable interrupt yes yes yes yes yes
On-chip debug (OCD) yes yes yes yes yes

 

Additional Benefits

Based on the Proven Xtensa Architecture


All Diamond Standard processors are based on the Xtensa Instruction Set Architecture, a 32-bit RISC architecture with: a 32-bit ALU; 16, 32 or 64 general-purpose registers; six special purpose registers; and 80 base instructions. The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions. These 16- and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance. One some processors, 64-bit VLIW is utilized when efficient, and these 2- or 3-issue instructions are modelessly intermixed with 16- and 24-bit instructions.

Rich Controller Features Set


All Diamond Standard processors use a rich interrupt architecture. Nine external interrupts at different hardware-defined priority levels provide system flexibility. Additionally, three timer interrupts and two software interrupts are available. For extreme time-critical applications, a non-maskable interrupt is included.

Ideal in Low-Power Applications


Tensilica uses clock gating and other architectural enhancements to keep power as low as possible. Clock gating stops unnecessary clocking activity to parts of the processor that are not in use on a particular clock cycle.

Bypass the Bus for High-Speed I/O


Most of Tensilica's Diamond Standard processors come with innovative ways to bypass the system bus for the fastest possible I/O – a feature available in no other 32-bit processor.

  1. GPIO ports – wires directly connect a Diamond processor to another Diamond or Xtensa processor or external RTL. Diamond processors use two 32-bit GPIOs for two-way high-speed communication, making them ideal to quickly convey control and status information.
  2. Queue interfaces – FIFO queues provide a high-speed mechanism to transfer streaming data. The data is always available without the need to load or store the data before or after computation.

For example, the Diamond Standard 570T includes both GPIO ports and queues. In the example below, the Diamond 570T is used to decode MP3 audio.

Direct Interfaces

The GPIO ports exchange control signals with the I2S interface logic. The FIFO queue sends the decoded audio stream to the DAC via the i2S interface logic, totally bypassing the bus for high-speed audio.

Optional AMBA Bridges


You have three integration choices:

  1. Tensilica's PIF – an advanced, high-performance system bus that services all external memories and peripheral devices in a typical Tensilica-based system. The PIF is capable of receiving inbound requests from an external master such as DMA. Sophisticated system bus features such as split-transactions and multiple outstanding requests are also defined by the PIF protocol.
  2. AMBA 2.0 AHB-Lite bridge – converts all signals between the AMBA and PIF protocols. All Diamond Standard controllers include pre-configured Verilog for the bridge for fast integration into AMBA-based designs.
  3. AMBA 3.0 AXI bus bridge – enables very simple hardware integration of a Tensilica core into an AMBA 3.0-based system.

Check out the complete listing of features in the Diamond Standard 106Micro, 108Mini, 212GP, 233L,or 570T product briefs.

Like The Diamonds, But Want More?

Our Diamond Standard processors are really Xtensa processors – just pre-configured with options many people like. But most of our customers are not satisfied with just these options. They like the Diamonds, but want just a little bit more (or a little bit less). That's the beauty of our system.

You can start with a Diamond processor and add what you want, or take away what you don't want, using our Xtensa processor development tools. Many options are simple click-box choices.

If you're not sure, just play around. See what the effects of little changes are on your software.

Check out our Xtensa processor section to see the wide world of options that awaits you.

Our Proven, Comprehensive HW and SW Design Environment

DPU design process

 

For Processor Designers

Tensilica delivers patented, proven tools that automate the process of generating a custom DPU along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Tensilica has the tools you need to create successful products.

View the complete set of tools for processor designers.

Software development process

For Software Developers

When you need to develop application code for Tensilica DPU, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. Tensilica's Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.

Documentation & Literature

製品概要

Title File Size Last Modified
Diamond Standard 106Micro Product Brief
The Diamond Standard 106Micro CPU is a small, low-power, cache-less 32-bit controller for embedded applications. It is ideal for designers migrating up from 8- or 16-bit controllers.
116 KB 06/26/2012
Diamond Standard 108Mini Product Brief
The Diamond Standard 108Mini is a small, fully synthesizable, cache-less 32-bit RISC core with tightly coupled local instruction and data memories, a rich interrupt architecture, and high arithmetic and DSP performance.
76 KB 06/28/2012
Diamond Standard 212GP Product Brief
The Diamond Standard 212GP is an area- and power-efficient, high-performance 32-bit RISC core with a local memory architecture that provides outstanding flexibility and performance.
75 KB 06/28/2012
Diamond Standard 233L Product Brief
The Diamond Standard 232L is a mid-range, area- and power-efficient 32-bit RISC core with a full-featured Memory Management Unit (MMU) for application processing using operating systems such as Linux.
130 KB 06/28/2012
Diamond Standard 570T Product Brief
The Diamond Standard 570T is a high-performance, high-throughput CPU that combines an efficient pipeline with a 3-issue VLIW architecture, enabling it to obtain leading performance levels on both control and DSP code.
129 KB 06/28/2012

ハードウェア/ソフトウェア開発ツール

Title File Size Last Modified
Xtensa Processor Developer's Toolkit Product Brief
Use the Xtensa Processor Developer’s Toolkit (PDK) to customize your Tensilica DPU. This Eclipse-based IDE has a full GUI that lets you pick your configuration options and add simple Verilog-like TIE for further customization.
228 KB 06/06/2012
Xtensa Software Developer's Toolkit Product Brief
If you need to develop application code for an Tensilica DPU,the Xtensa Software Developer’s Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process.
734 KB 06/06/2012

ホワイトペーパー

Title File Size Last Modified
Diamond Standard Core Family
An overview of this upward compatible family of efficient 32-bit RISC CPUs.
575 KB 03/27/2009
Processor Core Power Specs
It's what they don't tell you about power specs that matter.
185 KB 03/27/2009

Did You Know?

Did You Know?

Tensilica is the largest privately held semiconductor IP licensor?

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