Emulation Strategies

Tensilica's customers can deploy a variety of strategies for emulation of Xtensa-based SOC designs.

  • Some SoC designers use the RTL source code produced by the Xtensa Processor Generator, or the pre-optimized Xilinx NGO files automatically producted by the Xtensa Processor Generator, to support FPGA-based boards of their own design as part of a comprehensive SOC methodology.
  • Other Tensilica customers use commercial emulation systems in their SOC design process. EVE (Emulation and Verification Engineering) is Tensilica's recommended provider of high-capacity FPGA-based system emulators for SOC designs. EVE's ZeBu products are targeted for use in the system-integration phase of the design cycle where multiple logic blocks and embedded software must be verified together. EVE and Tensilica have partnered to provide seamless integration of Tensilica debug tools into the EVE development software environment.
  • For standalone Xtensa processor emulation for upper-level code porting and development on Xtensa-based designs, designers can use the Virtex-6 FPGA ML605 Xilinx-based development kit.


Did You Know?

Did You Know?

The LTE/HSPA/3G baseband chip in NTT Docomo’s newest mobile phones use multiple Tensilica DPUs, including the HiFi Audio DSP and the 'ConnX BBE Baseband DSP.