Industry's Most Powerful and Complete Processor Design Environment
Tensilica delivers patented, proven tools that automate the process of generating a custom Xtensa DPU along with matching software tools. These tools have been proven in hundreds of designs. Whether the core you want is for a simple controller or a complex multi-core DSP design, Tensilica DPUs can be tailored to meet your exact requirements.
To view complete, detailed specifications, please download the product brief for our Processor Developers' Toolkit.
The Design Cockpit
Our Xtensa Xplorer GUI serves as the cockpit for the entire design experience. You can profile your application code, identify "hot spots" that can benefit from acceleration, and make the changes necessary to speed up that code. Using a check-box menu within the GUI, you can configure DPUs to include features you need and remove features you don't. You can use our Verilog-like TIE language to further customize the processor, which often gives 10 to 100 times better performance.
Profile, Compare and Save Customizations
You can profile, compare and save different versions of your DPUs, so you can pick the right one for your application. Use the ISS or TurboXim for simulations, and model and simulate multiple processor subsystems using our XTensa Modeling Protocol (XTMP) or XTensa SystemC (XTSC) modeling. Xtensa Xplorer serves as the gateway to our Xtensa Processor Generator - a Cloud-based process that creates the automatically verified DPU to match all the options you defined, plus the matching software tool chain.
Learn More About This Powerful Toolset
The HW Design Flow
Configure the Processor to Your Specifications
It's as easy as checking a box or using a drop-down menu to pick the options - among hundreds of options - for your application. You start with a base DPU, then add just the features you need - and avoid the features you don't - so you get the lowest power, most efficient DPU.
Basic configuration options include processor interfaces, byte ordering, interrupts, arithmetic options, floating point, bridges, memory subsystem options, and much more.
Our Xtensa LX processor includes additional configuration options including our HiFi Audio DSPs, ConnX Vectra DSP entine, ConnX Baseband engines and more.
Use TIE for Further Customizations
The Verilog-like TIE (Tensilica Instruction Extension) language offers a wide range of flexibility in adding multi-cycle pipelined execution units, register files, SIMD arithmetic and logic units, creating wide (up to 512-bit) load/store instructions, and adding adding designer-defined I/O Ports, Queues, and Lookups. Additionally, your Xtensa LX processor can become a multi-issue VLIW processor. See our white papers for examples and ideas.
As you're designing your DPU, our Xtensa Xplorer IDE gives you lots of feedback on your design. You can see the impact on gate count (per instruction and for each register file or user state) and power consumption of any changes you make. We also provide a sophisticated pipeline viewer to help visualize the performance impact of TIE instructions. And you can save several different configurations as you're doing your exploring, then pick the best one for production. Xtensa Xplorer helps you create performance charts to visually compare different configurations.
Xtensa ISS and TurboXim Fast Functional Simulators
Use our ISS to analyze, debug and tune the performance of application software before committing the design to silicon. It's an instruction-count=accurate and pipeline-accurate model of your customized DPU. The ISS can provide cycle counts and performance summary information, as well as generate memory and exeucution traces and profiling data. This helps you compare profiles of different customizations to help you pick the very best one.
The optional TurboXim fast functional simulator achieves speeds that are 40 to 480 times faster than the cycle-accurate ISS. It enables simulations of DPU software at speeds similar to an FPGA prototype or emulation environment and at a meaningful fraction of the speed that the DPU will run on the actual target SoC. The TurboXim simulator, therefore, is extremely useful for software development and functional verification. TurboXim can be used with the ISS for hybrid simulations.
Efficient SoC Modeling
Tensilica offers two processor models intended for your use in SOC virtual prototypes: XTMP (XTensa Modeling Protocol) for modeling in C and XTSC (XTensa SystemC) for modeling in SystemC. XTSC offers co-simulation with Verilog using its pin-level modeling capabilities. Both models are powerful additions to Tensilica's software development toolkit. Running up to 100 times faster than RTL simulators, the XTMP/XTSC environments sccelerate software development and SOC design. Both simulations give you the ability to rapidly explore SOC partitioning alternatives and HW/SW performance tradeoffs.
XTMP and XTSC allow memory modeling of both local and system memory. System memory can have programmable latencies specified for different transaction types, allowing an accurate system simulation for analyzing performance tradeoffs. Memory-mapped peripherals may be included in an XTMP/XTSC system simulation, and functions are provided to connect the DPU to peripheral devices.
An XTMP or XTSC simulation runs in a multi-threaded environment, with each processor running in its own thread. A separate debugger is connected to each core for full visibility, and core threads can be run asynchronously or synchronized through events. Another option is to run all cores in lock-step, cycle-by-cycle mode. If one core stops on a break, all cores stop until it resumes. XTMP and XTSC have many of options for implementing, controlling and displaying results of system simulations deploying multiple cores, memories, and user-defined devices.