Learn More About Tensilica's Hardware and Software Design Tools

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製品ドキュメント

Title File Size Last Modified
Xtensa Processor Developer's Toolkit Product Brief
Use the Xtensa Processor Developer’s Toolkit (PDK) to customize your Tensilica DPU. This Eclipse-based IDE has a full GUI that lets you pick your configuration options and add simple Verilog-like TIE for further customization.
228 KB 06/06/2012
Xtensa Software Developer's Toolkit Product Brief
If you need to develop application code for an Tensilica DPU,the Xtensa Software Developer’s Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process.
734 KB 06/06/2012

ホワイトペーパー

Title File Size Last Modified
Everything You wanted to Know About SOC Memory But were Afraid to Ask
An in-depth look at memory concerns in SOC design.
731 KB 03/27/2009
How to Increase ASICs and SOC Computational Performance with Long-Word Processors
Learn how FLIX technology allows designers to accelerate a broader class of "hot spots" in embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.
101 KB 03/27/2009
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
Wire-based interfaces are familiar to many RTL designers and allow Tensilica's processors to substitute for hardware blocks without even changing the block-interface ("pin") definitions of existing RTL blocks.
63 KB 03/27/2009
Avoid Bus Bottlenecks and Get More Performance from Your ASIC and SOC Designs by Using High-Speed, On-Chip I/O
Innovative ways to get around the biggest performance bottleneck when using a processor in your SOC design - the main bus.
111 KB 03/27/2009
TIE - The Fast Path to High Performance Embedded SOC Processing
TIE, Tensilica's Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.
143 KB 05/12/2009
Using Processors in the SOC Dataplane
To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand.
202 KB 05/19/2009
The What, Why and How of Customizable Dataplane Processors (DPUs)
What is a DPU? What can DPUs do? Why would anyone want to use this type of processor? How can a DPU be used instead of creating hand-coded RTL hardware?
98 KB 09/29/2010
Optimize SOC Performance Using Memory Tuning and System Simulation
Memory tuning lets you choose memory-related parameters for each on-chip processor core to balance system performance, processor area, and memory size by exploring a target application's sensitivity to these memory system issues.
145 KB 02/23/2011


Did You Know?

Did You Know?

Tensilica is the largest privately held semiconductor IP licensor?