Learn More About Tensilica's DPUs



Xtensa DPU製品概要

Title File Size Last Modified
Xtensa LX4 Product Brief
Tensilica’s high-performance Xtensa LX4 DPU is ideal for handling complex compute-intensive signal processing applications. It features flexible I/Os that bypass the main system bus plus wide data fetches for maximum throughput.
580 KB 06/05/2012
Xtensa X9 Product Brief
Tensilica’s Xtensa 9 DPU is a highly efficient, ultra-low-power 32-bit controller. It can easily be extended to out-perform any other embedded processor for a specific application using a combination of configurable options and custom instructions.
352 KB 06/05/2012


Title File Size Last Modified
Diamond Standard 106Micro Product Brief
The Diamond Standard 106Micro CPU is a small, low-power, cache-less 32-bit controller for embedded applications. It is ideal for designers migrating up from 8- or 16-bit controllers.
116 KB 06/26/2012
Diamond Standard 108Mini Product Brief
The Diamond Standard 108Mini is a small, fully synthesizable, cache-less 32-bit RISC core with tightly coupled local instruction and data memories, a rich interrupt architecture, and high arithmetic and DSP performance.
76 KB 06/28/2012
Diamond Standard 212GP Product Brief
The Diamond Standard 212GP is an area- and power-efficient, high-performance 32-bit RISC core with a local memory architecture that provides outstanding flexibility and performance.
75 KB 06/28/2012
Diamond Standard 233L Product Brief
The Diamond Standard 232L is a mid-range, area- and power-efficient 32-bit RISC core with a full-featured Memory Management Unit (MMU) for application processing using operating systems such as Linux.
130 KB 06/28/2012
Diamond Standard 570T Product Brief
The Diamond Standard 570T is a high-performance, high-throughput CPU that combines an efficient pipeline with a 3-issue VLIW architecture, enabling it to obtain leading performance levels on both control and DSP code.
129 KB 06/28/2012


Title File Size Last Modified
HiFi 2 & HiFi EP Audio/Voice DSP Product Brief
Tensilica’s HiFi 2 and HiFi EP Audio/Voice DSPs provide proven, fully optimized approaches to embedding multi-standard audio into SOC designs.
233 KB 06/06/2012


Title File Size Last Modified
IVP Imaging/Video DSP Product Brief
The IVP imaging/video DSP includes a unique instruction set tuned for multi-frame image capture and video pre- and post-processing algorithms, as well as video stabilization, HDR for image and video, object and face recognition and tracking, low-light enhancement, digital zoom and gesture recognition.
157 KB 02/11/2013


Title File Size Last Modified
ConnX BBE16 (Baseband Engine) Product Brief
The ConnX BBE16 Baseband Engine is a high performance 16-MAC, 8-way SIMD, 3-issue VLIW DSP designed for use in next-generation communication baseband processors in LTE and 4G cellular radios and multi-standard broadcast receivers.
136 KB 06/28/2012
ConnX BBE32UE Product Brief
The ConnX BBE32UE is ideal for LTE-Advanced and multi-standard PHY user equipment systems with its core vector pipeline made of 32 MACs.
135 KB 06/28/2012
ConnX BBE64 (Baseband Engine) DSP
The ConnX BBE64 Baseband Engine is ideal for the demands of LTE-Advanced with its 32-way SIMD, 4-issue VLIW processing pipeline and 64 MACs.
241 KB 06/28/2012
ConnX BSP Bit-Stream Processor Product Brief
The ConnX BSP3 is a high-performance DPU optimized for processing and manipulation of bit streams, including operations for CRC, interleavers, scramblers and more.
140 KB 06/28/2012
ConnX SSP16 Soft Stream Processor
The ConnX SSP16 DPU is optimized for processing streams of soft bits, which are 4- to 8-bit representations of transmitted bits generated by the demodulator in the receive chain. It combines as 16-way SIMD, 3-slot VLIW pipeline optimized for 10- and 8-bit processing.
146 KB 06/28/2012
ConnX Turbo16MS
The ConnX Turbo16MS DPU is specifically designed for decoding LTE Turbo codes on data streams of up to 150 Mbps and HSPA+ data streams of up to 85 Mbps. It uses parallel execution for very high bandwidth computation.
257 KB 06/28/2012
ConnX D2 DSP Engine Product Brief
The ConnX D2 option adds dual 16-bit multiply-accumulate (MAC) units and a 40-bit register file to the base RISC architecture of the Xtensa LX processor. The ConnX D2 engine utilizes two-way SIMD (single instruction, multiple data) instructions to provide high performance on vectorizable C code.
175 KB 06/29/2012
ConnX Vectra LX DSP Engine Product Brief
The ConnX Vectra LX DSP engine isthe 4-MAC member of Tensilica's DSP family, Ideal application areas include: smart meters, short-range wireless, broadband modems, broadcast demodulation, and wire-line communications.
368 KB 08/30/2012


Title File Size Last Modified
Xtensa Processor Developer's Toolkit Product Brief
Use the Xtensa Processor Developer’s Toolkit (PDK) to customize your Tensilica DPU. This Eclipse-based IDE has a full GUI that lets you pick your configuration options and add simple Verilog-like TIE for further customization.
228 KB 06/06/2012
Xtensa Software Developer's Toolkit Product Brief
If you need to develop application code for an Tensilica DPU,the Xtensa Software Developer’s Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process.
734 KB 06/06/2012

Did You Know?

Did You Know?

Tensilica licensees have built over 700 DPU core variants in silicon?