White Papers


TitleFile SizeLast Modified
Optimizing a DSP Architecture For Wireless Baseband
The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations.
208 KB 08/18/2009
Cut DSP Development Time
The magic is in the compiler technology. Learn how an advanced compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code.
228 KB 08/21/2009
Microprocessor Report Reviews ConnX BBE64
See what the insider's guide to microprocessor hardware has to say about BBE64.
305 KB 04/11/2011
Tensilica Xtensa LX Processor with Vectra LX
This BDTI report evaluates the highest performance DSP core BDTI has tested.
170 KB 06/14/2012


TitleFile SizeLast Modified
Everything You Wanted to Know About Blu-ray Audio, but were afraid to hear
Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.
989 KB 03/27/2009
How to Manage Video Frame-Processing Time Deviations in ASIC and SOC Video Processors
HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.
182 KB 03/27/2009
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC
This paper explains the benefits of using a programmable processor-based solution for audio processing in SOC designs, as well as the disadvantages of using a RISC or other general-purpose core. It explains the 300 audio-specific instructions added to make the HiFi 2 Audio DSP much more efficient than a standard RISC processor to handle audio processing tasks.
125 KB 03/27/2009
How to Add Low-Power, Multi-Codec, Digital Video and Audio to Your Next ASIC or SOC Design
This white paper reviews digital video compression basic including the different types of algorithms used, a simple block diagram of the steps required for video compression and decompression, elements of a hardware video processors, task allocation for H.264 decoding, how to pass information to and from a video processor, and what a SOC design using a video processor might look like.
229 KB 03/27/2009
Seven Critical Questions to Ask When Selecting a Digital Audio Solution for Your Next Mobile SOC Design
The complexity of delivering a mobile audio IP solution to SOC designers causes design teams to ask many, many questions before choosing an audio core and associated codecs. That's a good thing. The selection process is complex, and the more information you have before making the decision, the better. Experience shows that design teams' questions about mobile audio solutions fall into seven broad categories.
36 KB 03/22/2011

General Information

TitleFile SizeLast Modified
Xtensa Architecture White Paper
More about the architecture behind all of Tensilica's processor cores and why they help deliver the lowest power and highest performance and code density in the industry.
529 KB 03/27/2009
Exploiting Core's Law: Get "More than Moore" Productivity From your ASIC and SOC Design Teams
Programmability vs efficiency trade-offs are examined for ASICs, and suggestions are made for an improved ASIC design methodology using processors as basic building blocks.
704 KB 03/27/2009
How to Avoid the Traps and Pitfalls of SOC Design
Chances are pretty good that your current SOC design approach is making your job much harder than it needs to be.
1200 KB 03/27/2009
10 Tips for Successful SOC Design
10 tips for your team find the right path to a successful SOC design.
47 KB 03/27/2009
Everything You wanted to Know About SOC Memory But were Afraid to Ask
An in-depth look at memory concerns in SOC design.
731 KB 03/27/2009
How to Increase ASICs and SOC Computational Performance with Long-Word Processors
Learn how FLIX technology allows designers to accelerate a broader class of "hot spots" in embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.
101 KB 03/27/2009
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
Wire-based interfaces are familiar to many RTL designers and allow Tensilica's processors to substitute for hardware blocks without even changing the block-interface ("pin") definitions of existing RTL blocks.
63 KB 03/27/2009
Avoid Bus Bottlenecks and Get More Performance from Your ASIC and SOC Designs by Using High-Speed, On-Chip I/O
Innovative ways to get around the biggest performance bottleneck when using a processor in your SOC design - the main bus.
111 KB 03/27/2009
Processor Core Power Specs
It's what they don't tell you about power specs that matter.
185 KB 03/27/2009
A Processor and DSP IP Selection Checklist
A useful checklist of questions to ask yourself, your team, and any processor IP providers you contact before your next SOC design project.
59 KB 04/08/2009
TIE - The Fast Path to High Performance Embedded SOC Processing
TIE, Tensilica's Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.
143 KB 05/12/2009
Using Processors in the SOC Dataplane
To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand.
202 KB 05/19/2009
The What, Why and How of Customizable Dataplane Processors (DPUs)
What is a DPU? What can DPUs do? Why would anyone want to use this type of processor? How can a DPU be used instead of creating hand-coded RTL hardware?
98 KB 09/29/2010
Optimize SOC Performance Using Memory Tuning and System Simulation
Memory tuning lets you choose memory-related parameters for each on-chip processor core to balance system performance, processor area, and memory size by exploring a target application's sensitivity to these memory system issues.
145 KB 02/23/2011
Seven Reasons to Customize a Processor Core
If you have more than simple control tasks, we give you ten good reasons why you should consider customizing your core in your next SOC design.
53 KB 10/08/2012

Diamond Standard Processor Cores

TitleFile SizeLast Modified
Diamond Standard Core Family
An overview of this upward compatible family of efficient 32-bit RISC CPUs.
575 KB 03/27/2009
Processor Core Power Specs
It's what they don't tell you about power specs that matter.
185 KB 03/27/2009

Did You Know?

Did You Know?

Qualcomm Atheros uses Tensilica DPUs in their high-volume, ultra-low-power GPS, WiFi and Bluetooth designs.